The present invention relates generally to semiconductor memory devices, and, more particularly, to a vertically integrated DRAM cell in which a transistor may be positioned directly above and vertically aligned to a deep trench capacitor.
A DRAM cell may typically include a deep trench capacitor electrically coupled to a transistor. In general, a capacitor may include two electrodes separated by some barrier (e.g. node dielectric) used to isolate the two electrodes from one another. A deep trench capacitor may typically be formed in a semiconductor-on-insulator substrate. The semiconductor-on-insulator substrate may have an SOI layer stacked on top of a buried oxide layer and the buried oxide layer stacked on top of a base substrate. The base substrate generally being n-doped silicon and the SOI layer generally being p-doped silicon, or vice versa. A pad layer or hardmask may also be located atop the semiconductor-on-insulator substrate. The deep trench capacitor may be formed through the pad layer and into all layers of the semiconductor-on-insulator substrate. In such cases, the base substrate may act as one of the capacitor's two electrodes while a conductive layer or an inner electrode may act as the other electrode.
The transistor may include a typical field effect transistor which may be positioned on the SOI layer and adjacent to the deep trench capacitor. The transistor may be electrically coupled to the deep trench capacitor using a strap. More specifically, the inner electrode of the deep trench capacitor may typically be electrically coupled to a source-drain region of the transistor.